1. Field of the Invention
This invention relates to a signal generating apparatus and, more particularly, to a signal generating apparatus using a phase locked loop (PLL) circuit for causing a voltage controlled oscillator (VCO) included in the PLL circuit to generate, in a series of steps, and in a substantially continuous manner, signals having desired frequencies within a predetermined frequency bandwidth.
2. Description of the Related Art
A signal generating apparatus which uses a PLL circuit is an example of a known conventional signal generating apparatus which can generate signals in the manner described above.
FIG. 1 shows an example of this type of conventional signal generating apparatus in which an output signal from voltage controlled oscillator 11, contained in the PLL circuit, and a local oscillation signal (frequency fL) from local oscillator 20 are mixed with each other by mixer 12, and the resulting composite signal is fed back to phase detector 14 through low-pass filter 13. In phase detector 14, the phases of the composite signal having frequency fr2 and a reference signal having frequency fr1 (=n.times..DELTA.f) (to be referred to hereinafter simply as composite signal fr2 and reference signal fr1) are compared with each other, and as a result of this comparison, a DC voltage signal corresponding to the phase difference is supplied to voltage controlled oscillator 11, through DC amplifier 15 and loop filter 16, this DC voltage signal controlling the oscillation frequency of voltage controlled oscillator 11. In this way, a signal having desired frequency fv (=fL+fr1) is generated from voltage controlled oscillator 11.
In the case described above, reference signal fr1 is a high-precision signal supplied from reference signal generator 10. Reference symbol n denotes a frequency index of a reference signal; and .DELTA.f, a fixed frequency between indexes. For example, when signals are to be generated within the frequency bandwidth of 520 to 1,070 MHz, each value is set as n=1 to 11 and .DELTA.f=50 MHz.
In the case described above, the generation of a 520-MHz signal will be described below.
When a frequency of 520 MHz is set in frequency setting section 19a, by means of a key input operation, controller 19, with ALU section 19b, commands reference signal generator 10 to generate reference signal fr1=1.times.50=50 MHz by setting switch SW, of reference signal generator 10, at position n=1, in accordance with the relationship between fv, n, and fr1 as shown in FIG. 2, and commands local oscillator 20 to generate local oscillation signal fL=fv-fr1=520-50=470 MHz, based on fv=fL+fr1.
With this operation, the PLL circuit functions such that a phase locked relationship is established between reference signal fr1 and composite signal fr2 (or output signal fv and local oscillation signal fL) at a point where composite signal fr2 has always frequency n.times..DELTA.f, thereby generating signal having desired frequency fv.
When a 1,070-MHz signal is to be generated, switch SW is set at position n=11 so as to set values as fr1=11.times.50=550 MHz, and fL=1,070-550=520 MHz.
However, in the signal generating apparatus using the conventional PLL circuit described above, when signals having frequencies with predetermined steps within a relatively wide bandwidth of 520 to 1,070 MHz are substantially continuously generated, the following problem is posed.
Since the number of frequency indexes n of reference signals is increased, a large number of reference signal sources (11 sources in the above example) for a wide frequency bandwidth are required.
This drawback interferes with the demands for a smaller size and lower cost required in current signal generating apparatuses.
One of the reasons why the number of frequency indexes n of reference signals is increased in the signal generating apparatus using the PLL circuit, as described above, is found in the problem of dead band of the phase detector in the PLL circuit. More specifically, this phase detector cannot be operated as a phase detector near the point where the frequency of an output signal from the mixer becomes zero, i.e., between the DC component and the low-frequency component band near substantially a DC component. For this reason, in order to evade this dead band, the PLL circuit must be arranged, as a whole, such that a predetermined frequency displacement is constantly provided so as not to cause an output signal from the mixer to become a DC component. This arrangement increases the number of frequency indexes n of reference signals. As described later, such speculation presents to the inventor of the present invention objects to be achieved. In addition, it is the first step to achieve the objects. Note that these objects include not only a decrease in the number of frequency indexes n of reference signals but also prevention of degradation in purity of signals and frequency stability of a signal generator unit and their improvement, as will be described in detail later.